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| 1. general description the tja1083 flexray node transceiver is comp liant with the flexray electrical physical layer specification v3.0.1 (see ref. 1 ). in order to meet jaspar the equirements, it implements the ?increased voltage amplitude trans mitter? functional class. it is primarily intended for communication systems operating at between 2.5 mbit/s and 10 mbit/s, and provides an advanced interface between the protocol controlle r and the physical bus in a flexray network. the tja1083 offers an opti mized solution for elec tronic control unit (ecu) applications that do not need en hanced power management and are typically switched by the ignition or activated by a dedicated wake-up line. the tja1083 provides a differential transmit capability to the network and a differential receive capability to the fl exray controller. it offers excellent electromagnetic compatibility (emc) pe rformance as well as high el ectrostatic discharge (esd) protection. the tja1083 actively monitors system perf ormance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. 2. features and benefits 2.1 optimized for time trig gered communication systems ? compliant with electrical physic al layer specification v3.0.1 ? meets jaspar requirements asdescribedin the ? busdriverincreasedvoltage amplitudetransmitter ? functionalclass ? automotive product qualificatio n in accordance with aec-q100 ? data transfer rates from 2.5 mbit/s to 10 mbit/s ? supports 60 ns minimum bit time at 400 mv differential input voltage ? very low electromagnetic emission (eme) to support unshielded cable ? differential receiver with high common-mode range for excellent electromagnetic immunity (emi) ? auto i/o level adaptation to host controller supply voltage v io ? can be used in 14 v, 24 v and 48 v powered systems ? instant transmitter shut-down interface (bge pin) 2.2 low-power management ? very low current consumption in standby mode ? remote wake-up via a wake-up pattern or dedicated flexray data frames on the bus lines tja1083 flexray node transceiver rev. 1 ? 10 october 2012 product data sheet
tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 2 of 41 nxp semiconductors tja1083 flexray node transceiver 2.3 diagnosis and robustness ? enhanced supply voltage monitoring for v cc and v io ? two error diagnosis modes: ? status register readout via the serial peripheral interface (spi) ? simple error indication via pin errn ? overtemperature detection ? short-circuit detection on bus lines ? power-on flag ? clamping diagnosis for pins txen and bge ? bus pins protected against ? 6 kv esd pulses according to iec61000-4-2 and ? 8 kv according to hbm ? bus pins protected against transients in automotive environment (according to iso 7637 class c) ? bus pins short-circuit proof to battery voltage (14 v, 24 v and 48 v) and ground ? maximum differential voltage between pins bp or bm and any other pin of ? 60 v ? bus lines remain passive when the transceiver is not powered ? no reverse currents from the digital input pins to v io or v cc when the transceiver is not powered 2.4 functional classes according to fl exray electrical physical layer specification v3.0.1 ? bus driver - increased voltage amplitude transmitter ? bus driver - bus guardian control interface ? bus driver - logic level adaptation ? bus driver - remote wake-up 3. ordering information table 1. ordering information type number package name description version TJA1083TT tssop14 plastic thin shrink small outli ne package; 14 leads; body width 4.4 mm sot402-1 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 3 of 41 nxp semiconductors tja1083 flexray node transceiver 4. block diagram fig 1. block diagram v cc undervoltage detection v io undervoltage detection txen timeout i/o i/o state machine over- temperature detection transmitter i/o activity detection bus error mux 13 12 txd txen v io v cc 2 3 1 spi sdo scsn sclk 8 9 7 rxd 4 11 gnd 14 i/o i/o i/o bge stbn errn 6 10 5 bp bm i/o low-power receiver normal receiver 015aaa242 i/o i/o i/o tja1083 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 4 of 41 nxp semiconductors tja1083 flexray node transceiver 5. pinning information 5.1 pinning 5.2 pin description 6. functional description 6.1 power modes the tja1083 features three power modes: no rmal, standby and power-off. normal and standby modes can be selected via the stbn input (high for normal mode) once the transceiver has been powered up. see table 3 for a detailed description of pin signaling in the three power modes. fig 2. pin configuration TJA1083TT v io v cc txd bp txen bm rxd gnd bge errn stbn scsn sclk sdo 015aaa134 1 2 3 4 5 6 7 8 10 9 12 11 14 13 table 2. pin description symbol pin type description v io 1 p supply voltage for v io voltage level adaptation txd 2 i transmit data input; internal pull-down txen 3 i transmitter enable input; when high transmitter di sabled; internal pull-up rxd 4 o receive data output bge 5 i bus guardian enable input; wh en low transmitter disabled; internal pull-down stbn 6 i mode control input; transceiver in normal mode when high; internal pull-down sclk 7 i spi clock signal; internal pull-up sdo 8 o spi data output scsn 9 i spi chip select input; internal pull-up/pull-down errn 10 o error diagnosis output and wake-up indication gnd 11 p ground bm 12 i/o bus line minus bp 13 i/o bus line plus v cc 14 p supply voltage (+5 v) tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 5 of 41 nxp semiconductors tja1083 flexray node transceiver [1] the wake flag is set if a valid wake-up event is detected while switching to standby mode. [2] the wake flag is set if a valid wake-up event is detected. [3] v uvd(vcc) > v cc > v th(det)por . [4] pins errn and rxd reflect the state of the wake flag prior to the v cc undervoltage event. [5] the internal signals at pins stbn, bge and txd are set low; t he internal signals at pins txen, sclk and scsn are set high. [6] except when v cc = 0; in this case bp and bm are floating. 6.1.1 normal mode in normal mode, the transceiver transmits and receives data via the bus lines bp and bm. the transmitter and the normal receiver are enabled, along with the undervoltage detection function. the timing diagra m for normal mode is illustrated in figure 3 . table 3. pin signaling in the different power modes mode stbn uv at v io uv at v cc errn rxd sdo biasing bp, bm uv-det trans- mitter low- power receiver low high low high normal high no no error flag set error flag reset bus data _0 bus data_1 or idle high- impedance (in simple error indication mode) or enabled (in spi mode) v cc / 2 enabled enabled enabled [1] standby low no no wake flag set wake flag reset wake flag set wake flag reset gnd disabled enabled [2] low no yes [3] wake flag set [4] wake flag reset [4] wake flag set [4] wake flag reset [4] disabled high no yes [3] error flag set error flag reset wake flag set [4] wake flag reset [4] xyes [5] no low low high- impedance enabled [2] xyes [5] yes [3] low low disabled power-off x x [5] yes high- impedance high gnd [6] disabled disabled tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 6 of 41 nxp semiconductors tja1083 flexray node transceiver ta b l e 4 describes the behavior of the transmitte r in normal mode, when the temperature flag (temp high) is not set and with no time -out on pin txen. transmitter behavior is illustrated in figure 13 . the transmitter is activated during the first low level on pin txd while pin bge is high and pin txen is low. in normal mode, the normal receiver output is connected directly to pin rxd (see ta b l e 5 ). receiver behavior is illustrated in figure 14 . when v io and v cc are within their operatin g ranges, pin errn indicates the status of the error flag. see section 6.8 for a detailed description of error signaling in normal mode. fig 3. timing diagram for normal mode 015aaa002 txd bge rxd bm bp txen table 4. transmitter operation in normal mode bge txen txd bus state transmitter l x x idle transmitter is disabled x h x idle transmitter is disabled h l h data_1 transmitter is enabled; the bus lines are actively driven; bp is driven high and bm is driven low h l l data_0 transmitter is enabled; the bus lines are actively driven; bp is driven low and bm is driven high table 5. behavior of normal receiver in normal mode bus state rxd data_0 l data_1 h idle h tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 7 of 41 nxp semiconductors tja1083 flexray node transceiver 6.1.1.1 bus activity and idle detection in normal mode, bus activity and bus idle are detected as follows: ? bus activity is detected when the absolute differential voltage on the bus lines is higher than ? v i(dif)det(act) ? for t det(act)(bus) : ? if the differential voltage on the bus lines is lower than v il(dif) after bus activity has been detected, pin rxd switches low. ? if the differential voltage on the bus lines is higher than v ih(dif) after bus activity has been detected, pin rxd remains high. ? bus idle is detected when the absolute differential voltage on the bus lines is lower than ? v i(dif)det(act) ? for t det(idle)(bus) . this results in pin rxd being switched high or staying high. 6.1.2 standby mode standby mode is a low-power mode featuring very low current consumption. in standby mode, the transceiver is unable to transmit or receive data since both the transmitter and the normal receiver are switched off. the low-power receiver is activated to monitor the bus for wake-up activity, provided an undervoltage has not been detected on pin v cc . the low-power receiver is deactivated if an undervoltage is detected on pin v cc - with the result that the wake flag is not set if a wake-up pattern or dedicated data frame is received. pins errn and rxd indicate the status of the wake flag when v io and v cc are within their operating ranges. see ta b l e 3 for a description of pi ns errn and rxd when an undervoltage is detected on pin v io or pin v cc . the status register cannot be read via the spi interface if an undervoltage is detected on pin v io . the bge input has no effect in standby mode. 6.1.3 power-off mode the transmitter and the two receivers (normal and low-power) are deactivated in power-off mode. as a result, the wake flag is not set if a wake-up pattern or dedicated data frame is received . if the voltage at v cc rises above v th(rec)por , the transceiver switches to standby mode and the digital section is reset. if v cc subsequently drops below v th(det)por , the transceiver reverts to power-off mode (see section 6.2 ). the status register cannot be read vi a the spi interface in power-off mode. 6.1.4 state transitions figure 4 shows the tja1083 state transition di agram. the timing diagram for the errn indication signal during transitions betwe en normal and standby modes, when the error flag is set and the wake flag is not set, is illustrated in figure 5 and described in ta b l e 6 . tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 8 of 41 nxp semiconductors tja1083 flexray node transceiver fig 4. state transitions diagram fig 5. state transitions timing (error flag set) standby normal stbn -> low or uv vcc flag set or uv vio flag set (stbn -> high while uv flags cleared) or (uv flags cleared while stbn = high) power off v cc < v th(det)por v cc > v th(rec)por 015aaa004 20 s t d(norm-stb) t d(stb-norm) stbn errn 015aaa003 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 9 of 41 nxp semiconductors tja1083 flexray node transceiver [1] see table 7 for set and reset conditions of all flags. 6.2 power-up and power-down behavior 6.2.1 power-up the tja1083 has two supply pins: v cc (+5 v) and v io (for the voltage level adaptation). the ramp up of the different power supplies can vary, depending on the state or value of a number of signals and parameters. the power- up behavior of the tja1083 is not affected by the sequence in which power is supplied to these pins or by the voltage ramp up. as an example, figure 6 shows one possible power supply ramp-up scenario. the digital section of the tja1083 is supplied by v cc . the voltage on pin v cc ramps up before the voltage on pin v io . as long as the voltage on v cc remains below the power-on reset recovery threshold, v th(rec)por , the internal state ma chine is inactive and the transceiver is totally passive, remaining in power-off mode. as soon as the voltage rises above the v th(rec)por threshold, the internal state machine starts running, setting the pwon flag and switching the tja1083 to standby mode. this initializes the v cc and v io under-voltage flags to the set state (since both v cc and v io are actually in undervoltage state just after power-on). once both v io and v cc have reached their operating ranges, the under-voltage flags are reset. the operating mode is then determi ned by the level on stbn (the tja1083 switches to normal mode if stbn is high and remains in standby mode if stbn is low), provided v io and v cc are above their respective undervoltage recovery levels (v uvr(vio) and v uvr(vcc) ). table 6. state transitions ? indicates the action that initiates a transaction; 1 ?? and 2 ?? are the consequences of a transaction. transition uvv io flag [1] uvv cc flag [1] wake flag [1] pwon flag [1] stbn vcc level normal to standby cleared cleared cleared cleared ? lv cc > v uvd(vcc) ? set cleared cleared cleared h v cc > v uvd(vcc) cleared ? set cleared cleared h v uvd(vcc) > v cc > v th(det)por standby to normal cleared cleared 1 ? cleared 2 ? cleared ? hv cc > v uvd(vcc) ? cleared cleared 1 ? cleared 2 ? cleared h v cc > v uvd(vcc) cleared ? cleared 1 ? cleared 2 ? cleared h v uvd(vcc) > v cc > v th(det)por standby to power-off x set x x x ? v cc < v th(det)por power-off to standby x set x 1 ? set x ? v cc > v th(rec)por tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 10 of 41 nxp semiconductors tja1083 flexray node transceiver 6.2.2 power-down the behavior of the tj a1083 during power-down is illustrated in figure 7 . fig 6. power-up behavior (example) stbn v cc v io v uvr(vcc) v th(rec)por v uvr(vio) normal standby power-off errn rxd 015aaa005 fig 7. power-down behavior (example) v cc v io stbn rxd errn normal standby power-off v uvd(vcc) v th(det)por v uvd(vio) 015aaa006 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 11 of 41 nxp semiconductors tja1083 flexray node transceiver 6.3 remote wake-up 6.3.1 bus wake-up via wake-up pattern a valid remote wake-up event occurs when a wake-up pattern is received. a wake-up pattern consists of at least two cons ecutive wake-up symbols. a wake-up symbol comprises a data_0 phase lasting longer than t det(wake)data_0 followed by an idle phase lasting longer than t det(wake)idle , provided both wake-up symbols occur within a time span of t det(wake)tot (see figure 8 ). the transceiver also wakes up if data_1 phases are substituted for the idle phases. see ref. 1 for more details of the wake-up mechanism. 6.3.2 bus wake-up via dedicated flexray data frame the tja1083 wake flag is set when a dedicated data frame emulating a valid wake-up pattern, as shown in figure 9 , is received. the data_0 and data_1 phases of the emulated wake-up symbol are interrupted by the byte start sequence (bss) preceding each byte in the data frame. with a data rate of 10 mbit/s, the interruption has a maximum duration of 130 ns and does not prevent the transceiver from recognizing the wake-up pattern in the payload. for longer interruptions at lo wer data rates (5 mbit/s and 2.5 mbit/s), the wake-up pattern should be used (see section 6.3.1 ). the wake flag is not set if an inva lid wake-up pattern is received. see ref. 1 for more details on invalid wake-up patterns. fig 8. bus wake-up timing 0 v dif (mv) 0 -500 > t det(wake)data_0 > t det(wake)idle > t det(wake)idle > t det(wake)data_0 > t det(wake)data_0 > t det(wake)data_0 > t det(wake)idle > t det(wake)idle wake-up +500 015aaa007 0 -500 < t det(wake)tot wake-up pattern wake-up symbol wake-up symbol tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 12 of 41 nxp semiconductors tja1083 flexray node transceiver 6.4 bus error detection the tja1083 detects the following bus errors during transmission: ? short-circuit bp to bm at th e ecu connector or on the bus ? short-circuit bp to gnd at the ecu connector or on the bus ? short-circuit bm to gnd at th e ecu connector or on the bus ? short-circuit bp to v cc at the ecu connector or on the bus ? short-circuit bm to v cc at the ecu connector or on the bus the bus error flag is not set when a wake- up pattern or a flexray collision avoidance symbol (cas) is being transmitted or received. 6.5 fail silent behavior three mechanisms guarantee the ?fail silent? behavior of the tja1083: ? the txen clamped flag is set if pin txen goes low for longer than t detcl(txen) in normal mode; the transmitter is disabled. ? the bge clamped flag is set if pin bge goes high for longer than t detcl(bge) in normal mode; no action is taken. ? if a loss-of-ground occurs at the transceiver, resulting in the tja1083 switching to power-off mode, no current flows out of the digital input pins (txd, txen, bge, stbn, sclk, scsn); see table 3 for details of the behavior of the bus pins. 6.6 tja1083 flags the tja1083 has 11 status/error flags. these are described in ta b l e 7 . the duration of each interruption is 130 ns. the transition time from data_0 to data_1 and vice versa is about 20 ns. the tja1083 wake-up flag is set on receipt of the following frame payload: 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff fig 9. minimum bus pattern for bus wake-up via dedicated flexray data frame 015aaa139 v dif 0 v -2000 wake-up +2000 870 ns 870 ns 870 ns 870 ns 770 ns 130 ns 130 ns 130 ns 5 s 5 s 5 s 5 s tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 13 of 41 nxp semiconductors tja1083 flexray node transceiver [1] all flags, except for the pwon flag, are reset after a power-on reset. [2] if an undervoltage has not been detected on pin v cc . [3] if stbn = low. [4] if bge = high, the normal mode flag is set, the temp high flag is not set and the txen clamped flag is not set. [5] flag can only be set or reset in normal mode or on leaving normal mode. [6] if stbn = high. [7] if stbn = high in spi mode [8] the spi error flag is set when: a) more than 16 falling edges occur on pin sclk while pin scsn = low b) less than 16 falling edges occur on pin sclk while pin scsn = low. 6.7 tja1083 status register the tja1083 contains a 16-bit status register, of which bits s0 to s4 reflect the state of the status flags, bits s5 to s10 reflect the stat e of the error flags and bit s15 is a parity bit. all flags can be individually read out on pin sdo via a 16-bit spi interface when the transceiver is configured in spi mode. the status register bits are described in ta b l e 8 . table 7. tja1083 flags and set/reset conditions flag name flag type flag description set condition reset condition [1] consequence of flag set bus wake status flag indicates if a wake-up event has occurred wake-up event on bus in standby mode [2] transition to normal mode rxd ? low; errn ? low [3] normal mode status flag indicates if the transceiver is in normal mode entering normal mode leaving normal mode - transmitter enabled status flag indicates the transmitter status transmitter enabled [4] transmitter disabled - bge clamped status flag indicates if pin bge is clamped bge high for longer than t detcl(bge) [5] bge low [5] - pwon status flag indicates when the digital section is initialized v cc > v th(rec)por transition to normal mode - bus error error flag indicates if a bus error has been detected bus error detected [5] no bus error detected or positive edge on txen [5] errn ? low [6] temp high error flag indicates if the max. junction temperature has been reached t vj > t j(dis)(high) [5] txen = high while t vj < t j(dis)(high) [5] errn ? low [6] ; transmitter disabled txen clamped error flag indicates if pin txen is clamped txen low for longer than t detcl(txen) [5] txen = high [5] errn ? low [6] ; transmitter disabled uvv cc error flag indicates if there is an undervoltage at pin v cc v cc < v uvd(vcc) for longer than t det(uv)(vcc) v cc > v uvr(vcc) for longer than t rec(uv)(vcc) errn ? low [6] ; entering standby mode uvv io error flag indicates if there is an undervoltage at pin v io v io < v uvd(vio) for longer than t det(uv)(vio) v io > v uvr(vio) for longer than t rec(uv)(vio) errn ? low [6] ; entering standby mode spi error error flag indi cates if an spi error has occurred spi error detected [8] falling edge on scsn errn ? low [7] ; sdo goes to a high impedance state tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 14 of 41 nxp semiconductors tja1083 flexray node transceiver [1] also cleared during power-off. 6.8 error signaling the tja1083 provides two modes for error indication: ? simple error indication mode ? spi mode (default mode) spi mode is active on power-up. to switch to simple error indication mode, scsn must be held low (connected to gnd) and sclk held high (connected to v io ) for longer than t det(l)(sclk) (provided a v io undervoltage has not occurred). when the tja1083 is in simple error indication mode, a rising edge on scsn initiates a transition to spi mode (again provided a v io undervoltage has not occurred); see figure 10 . table 8. tja1083 status register status bit flag name set condition reset condition s0 bus wake bus wake flag set bus wake flag cleared s1 normal mode normal mode flag set normal mode flag cleared s2 transmitter enabled transmitter enabled flag set transmitter enabled flag cleared s3 bge clamped bge clamped flag set bge clamped flag cleared s4 pwon pwon flag set pwon flag cleared and successful readout [1] s5 bus error bus error flag se t bus error flag cleared and successful readout [1] s6 temp high temp high flag se t temp high flag cleared and successful readout [1] s7 txen clamped txen clamped flag set txen clamped flag cleared and successful readout [1] s8 uvv cc uvv cc flag set uvv cc flag cleared and successful readout [1] s9 uvv io uvv io flag set uvv io flag cleared and successful readout [1] s10 spi error spi error flag se t spi error flag cleared and successful readout [1] s11 reserved always low s12 reserved always high s13 reserved always low s14 reserved always high s15 parity bit odd parity of status bits even parity of status bits tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 15 of 41 nxp semiconductors tja1083 flexray node transceiver if a v io undervoltage condition is de tected, it is not possible to switch between spi mode and simple error indication mode. 6.8.1 spi mode the error flag information in the status regist er is latched in spi mode. this means that the status bit is reset once the status register has been completely read (provided the corresponding error flag has been reset). if an error condition is detected in normal mode, pin errn goes low (provided one of the error bits, s5 to s10, is set). pin errn goes high again once all the error bits have been reset. 6.8.2 simple error indication mode if an error condition is detected in normal mode, pin errn goes low once the relevant error flag has been set. pin errn stays stable for at least t errnl(min) and goes high again when all error conditions have been cl eared and all flags have been reset. error flags are not latched. it is not possible to read-out the status bits in this mode. 6.9 spi interface the tja1083 includes a 16-bit spi interface to enable a host to read the status register when the transceiver is in spi mode (see section 6.8 ). while pin scsn is high, the sd o output is in a high-impedance state. to begin a status register readout, the host must force pin sc sn low. this action causes the sdo pin to output a low level by default. the data on pin sdo is then shifted out on the rising edge of the clock signal on pin sclk. the status bits shifted out on pin sdo are ac tive high. the status bits are refreshed and pin sdo returned to a high-impedance state once the status register has been read successfully (after exactly 16 clock cycles) an d scsn has been forced high again. clock signals on sclk are ignored while scsn is high. the timing diagra m for the spi readout is illustrated in figure 11 . the slck period ranges from 500 ns to 100 ? s (10 kbit/s to 2 mbit/s). fig 10. timing diagram for configuration of error indication mode scsn (v) 0 v io t sclk (v) 0 v io t t det(l)(sclk) spi mode simple error indication mode spi mode 015aaa015 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 16 of 41 nxp semiconductors tja1083 flexray node transceiver if scsn remains low for longer than 16 clock cycles, it is recognized as an spi error. when this happens, the spi error flag is se t and pin sdo goes to a high-impedance state until the next falling edge on pin scsn. an spi error is also assumed if fewer than 16 clock cycles are received while scsn is low. if this happens, the spi error flag is set. all status bits are refreshed once the status register has been successfully read. when the transceiver is in simple error indication mode the sdo output is in a high-impedance state and pin scsn is in pu ll-down mode. in spi mode pin scsn is in pull-up mode. spi readout is not possible when the transc eiver has detected an undervoltage on v io . 7. limiting values fig 11. spi readout timing diagram scsn sclk sdo z l s0 s1 s2 s14 s15 z 01 02 03 15 16 t d(scsnlh-sdoz) t sclk t d(sclklh-sdodv) t d(scsnhl-sdol) 015aaa009 t spilead t spilag table 9. limiting values in accordance with the absolute maximum rating syst em (iec 60134). all voltages are referenced to gnd. symbol parameter conditions min max unit v cc supply voltage no time limit ? 0.3 +5.5 v v io supply voltage on pin v io no time limit ? 0.3 +5.5 v v errn voltage on pin errn no time limit ? 0.3 v io + 0.3 v v rxd voltage on pin rxd no time limit ? 0.3 v io + 0.3 v v sdo voltage on pin sdo no time limit ? 0.3 v io + 0.3 v v txen voltage on pin txen no time limit ? 0.3 +5.5 v v txd voltage on pin txd no time limit ? 0.3 +5.5 v v stbn voltage on pin stbn no time limit ? 0.3 +5.5 v v scsn voltage on pin scsn no time limit ? 0.3 +5.5 v v sclk voltage on pin sclk no time limit ? 0.3 +5.5 v v bge voltage on pin bge no time limit ? 0.3 +5.5 v v bp voltage on pin bp no time limit (with respect to pins bm and gnd) ? 60 +60 v tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 17 of 41 nxp semiconductors tja1083 flexray node transceiver [1] according to iso7637, test pulse 1, cl ass c; verified by an external test house. [2] according to iso7637, test pulse 2a, cl ass c; verified by an external test house. [3] according to iso7637, test pulse 3a, cl ass c; verified by an external test house. [4] according to iso7637, test pulse 3b, cl ass c; verified by an external test house. [5] in accordance with iec 60747-1. an alternative definition of t vj is: t vj =t amb +p? r th(j-a) , where r th(j-a) is a fixed value used in the calculation of t vj . the rating for t vj limits the allowable combinations of pow er dissipation (p) and ambient temperature (t amb ). [6] iec61000-4-2: c = 150 pf; r = 330 ? ; verified by an external test house; the test results were equal to or better than ? 6 kv (unaided). [7] hbm: c = 100 pf; r = 1.5 k ? . [8] mm: c = 200 pf; l = 0.75 ? h; r = 10 ? . [9] cdm: r = 1 ? . 8. thermal characteristics v bm voltage on pin bm no time limit (with respect to pins bp and gnd) ? 60 +60 v i i(errn) input current on pin errn no time limit; v io =0v ? 10 10 ma i i(rxd) input current on pin rxd no time limit; v io =0v ? 10 10 ma i i(sdo) input current on pin sdo no time limit; v io =0v ? 10 10 ma v trt transient voltage on pins bm and bp [1] ? 100 - v [2] -75 v [3] ? 150 - v [4] -100 v t stg storage temperature ? 55 +150 ?c t vj virtual junction temperature [5] ? 40 +150 ?c t amb ambient temperature ? 40 +125 ?c v esd electrostatic discharge voltage iec 61000-4-2 on pins bp and bm to ground [6] ? 6.0 +6.0 kv hbm on pins bp and bm to ground [7] ? 8.0 +8.0 kv hbm on any other pin [7] ? 4.0 +4.0 kv mm on all pins [8] ? 200 +200 v cdm on all pins [9] ? 1000 +1000 v table 9. limiting values ?continued in accordance with the absolute maximum rating syst em (iec 60134). all voltages are referenced to gnd. symbol parameter conditions min max unit table 10. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 130 k/w tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 18 of 41 nxp semiconductors tja1083 flexray node transceiver 9. static characteristics table 11. static characteristics all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? to 55 ? and c bus = 100 pf unless otherwise specified. all voltages are defined with respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit pin v cc i cc supply current standby mode with no undervoltage; t vj ? 85 ?c -2030 ? a standby mode with no undervoltage; t vj ? 150 ? c -2040 ? a power-off mode; t vj ? 85 ? c--3 0 ? a power-off mode; t vj ? 150 ? c--4 0 ? a normal mode; v bge =0vorv txen =v io -1122ma normal mode; v bge =v io ; v txen = 0 v -4060ma normal mode; v bge =v io ; v txen = 0; v; r bus > 10 m ? -2540ma v uvd(vcc) undervoltage detection voltage on pin v cc 4.45 - 4.729 v v uvr(vcc) undervoltage recovery voltage on pin v cc 4.47 - 4.749 v v uvhys(vcc) undervoltage hysteresis voltage on pin v cc 20 - 290 mv v th(det)por power-on reset detection threshold voltage 3.75 - 4.15 v v th(rec)por power-on reset recovery threshold voltage 3.85 - 4.25 v v hys(por) power-on reset hysteresis voltage 100 - 500 mv pin v io i io supply current on pin v io normal mode; v txen = v io ; v bge = v io ; r rxd > 10 m ? - - 1000 ? a normal mode; v txen = 0 v; v bge = v io ; r rxd > 10 m ? - - 1000 ? a standby mode with no undervoltage - 2.2 7 ? a power-off mode; v io = 5 v - 3 7 ? a v uvd(vio) undervoltage detection voltage on pin v io 2.55 - 2.774 v v uvr(vio) undervoltage recovery voltage on pin v io 2.575 - 2.799 v v uvhys(vio) undervoltage hysteresis voltage on pin v io 25 - 240 mv pin scsn v ih high-level input voltage 0.7v io -5.5v tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 19 of 41 nxp semiconductors tja1083 flexray node transceiver v il low-level input voltage ? 0.3 - 0.3v io v i ih high-level input current simple error indication mode; v scsn = 0.7v io 3-15 ? a i il low-level input current spi mode; v scsn = 0.3v io ? 15 - ? 3 ? a i r reverse current power-off mode; to v cc /v io ; v scsn = 5 v; v cc = v io = 0 v ? 50+5 ? a pin sclk v ih high-level input voltage 0.7v io -5.5v v il low-level input voltage ? 0.3 - 0.3v io v i ih high-level input current v sclk = v io ? 10+1 ? a i il low-level input current v sclk = 0.3v io ? 15 - ? 3 ? a i r reverse current power-off mode; to v cc /v io ; v sclk = 5 v; v cc = v io = 0 v ? 50+5 ? a pin stbn v ih high-level input voltage 0.7v io -5.5v v il low-level input voltage ? 0.3 - 0.3v io v i ih high-level input current v stbn = 0.7v io 3-15 ? a i il low-level input current v stbn = 0 v ? 10+1 ? a i r reverse current power-off mode; to v cc /v io ; v stbn = 5 v; v cc =v io = 0 v ? 50+5 ? a pin txen v ih high-level input voltage 0.7v io -5.5v v il low-level input voltage ? 0.3 - 0.3v io v i ih high-level input current v txen = v io ? 10+1 ? a i il low-level input current v txen = 0.3v io ? 300 - ? 50 ? a i r reverse current power-off mode; to v cc /v io ; v txen = 5 v; v cc = v io = 0 v ? 50+5 ? a pin bge v ih high-level input voltage 0.7v io -5.5v v il low-level input voltage ? 0.3 - 0.3v io v i ih high-level input current v bge = 0.6v io 3-15 ? a i il low-level input current v bge = 0 v ? 10+1 ? a i r reverse current power-off mode; to v cc /v io ; v bge = 5 v; v cc = v io = 0 v ? 50+5 ? a pin txd v ih high-level input voltage normal mode 0.6v io -5.5v v il low-level input voltage normal mode ? 0.3 - 0.4v io v i ih high-level input current v txd = 0.6v io 3-15 ? a i il low-level input current v txd =0v ? 10+1 ? a table 11. static characteristics ?continued all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? to 55 ? and c bus = 100 pf unless otherwise specified. all voltages are defined with respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 20 of 41 nxp semiconductors tja1083 flexray node transceiver i r reverse current power-off mode; to v cc /v io ; v txd = 5 v; v cc = v io = 0 v ? 50+5 ? a c i input capacitance with respect to all other pins at ground; v txd = 100 mv; f = 5 mhz [1] - - 10 pf pin rxd v oh high-level output voltage i oh(rxd) = ? 1.5 ma v io ? 0.4 - v io v v ol low-level output voltage i ol(rxd) = 1.5 ma - - 0.4 v i oh high-level output current v rxd = v io ? 0.4 v; v io =v cc ? 15 - ? 1.5 ma i ol low-level output current v rxd = 0.4 v 1.5 - 15 ma v o output voltage when undervoltage on v io ; r l = 100 k ? to gnd --500mv power-off mode; r l = 100 k ? to v io v io ? 500 - v io mv pin errn v oh high-level output voltage i oh(errn) = ? 100 ? av io ? 0.4 - v io v v ol low-level output voltage i ol(errn) = 200 ? a--0.4v i oh high-level output current v errn =v io ? 0.4 v; v io =v cc ? 1500 - ? 100 ? a i ol low-level output current v errn = 0.4 v 200 - 1700 ? a i l leakage current power-off mode; v errn ? v io ? 5-+5 ? a v o output voltage when undervoltage on v io ; r l = 100 k ? to gnd --500mv power-off mode; r l = 100 k ? to gnd --500mv pin sdo v oh high-level output voltage i oh(sdo) = ? 0.5 ma v io ? 0.4 - v io v v ol low-level output voltage i ol(sdo) = 0.8 ma - - 0.4 v i oh high-level output current v sdo = v io ? 0.4 v ? 8 ? 3 ? 0.5 ma i ol low-level output current v sdo = 0.4 v 0.8 3 9 ma i l leakage current high-impedance state; 0v tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 22 of 41 nxp semiconductors tja1083 flexray node transceiver [1] guaranteed by design. [2] v cm is the bp/bm common mode voltage. [3] z o(tx)(eq) = 50 ? ? (v bus(100) ? v bus(40) )/(2.5 ? v bus(40) ? v bus(100) ), where: v bus(100) = the differential output voltage on a load of 100 ? and 100 pf in parallel. v bus(40) = the differential output voltage on a load of 40 ? and100 pf in parallel, when driving a data_1. [4] r sc is the short-circuit resistance; voltage di fference between bus pins bp and bm is 60 v max. [5] r sc is the short-circuit resistance between bp and bm. [6] t sc is the minimum duration of the short-circuit r i(bm) input resistance on pin bm r bus = ? ? 10 20 40 k ? r i(dif)(bp-bm) differential input resistance between pin bp and pin bm r bus = ? ? 20 40 80 k ? i li(bp) input leakage current on pin bp power-off mode; v cc =v io =0 v; 0 v ? v bp ? 5v ? 50+5 ? a loss of ground; v bp =v bm =0v; all other pins connected to 16 v via 0 ? [1] ? 1600 - +1600 ? a i li(bm) input leakage current on pin bm power-off mode; v cc =v io =0 v; 0 v ? v bm ? 5v ? 50+5 ? a loss of ground; v bp =v bm =0v; all other pins connected to 16 v via 0 ? [1] ? 1600 - +1600 ? a v cm(bus)(data_0) data_0 bus common-mode voltage normal mode 0.4v cc 0.5v cc 0.65v cc v v cm(bus)(data_1) data_1 bus common-mode voltage normal mode 0.4v cc 0.5v cc 0.65v cc v ? v cm(bus) bus common-mode voltage difference normal mode; data_1 ? data_0 ? 250+25mv c i(bp) input capacitance on pin bp with respect to all other pins at ground; v bp = 100 mv; f = 5 mhz [1] - - 15 pf c i(bm) input capacitance on pin bm with respect to all other pins at ground; v bm = 100 mv; f = 5 mhz [1] - - 15 pf c i(dif)(bp-bm) differential input capacitance between pin bp and pin bm with respect to all other pins at ground; v bp = 100 mv; v bm = 100 mv; f = 5 mhz [1] --5pf z o(eq)tx transmitter equivalent output impedance normal mode; c bus = 100 pf; r bus =40 ? or 100 ? [3] 10 - 600 ? temperature protection t j(dis)(high) high disable junction temperature 180 - 200 ?c table 11. static characteristics ?continued all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? to 55 ? and c bus = 100 pf unless otherwise specified. all voltages are defined with respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 23 of 41 nxp semiconductors tja1083 flexray node transceiver 10. dynamic characteristics table 12. dynamic characteristics all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? and c bus = 100 pf unless otherwise specified. all voltages are defined wi th respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit pins bp and bm t d(txd-bus) delay time from txd to bus normal mode [1] [2] data_0 - - 60 ns data_1 - - 60 ns ? t d(txd-bus) delay time difference from txd to bus normal mode; between data_0 and data_1; normal mode [1] [2] ? 4- +4ns t d(bus-rxd) delay time from bus to rxd normal mode; c rxd = 25 pf; v cm = 2.5 v [3] [4] data_0 - - 75 ns data_1 - - 75 ns ? t d(bus-rxd) delay time difference from bus to rxd between data_0 and data_1; normal mode; c rxd = 25 pf; v cm = 2.5 v [3] [4] ? 5- 5 ns t d(txen-busidle) delay time from txen to bus idle normal mode; v txd = 0 v [5] - - 75 ns t d(txen-busact) delay time from txen to bus active normal mode; v txd = 0 v [5] - - 75 ns ?? t d(txen-bus) ? delay time difference from txen to bus (absolute value) normal mode; between txen to bus active and txen to bus idle; v txd = 0 v [6] [5] 50 ns t d(bge-busidle) delay time from bge to bus idle normal mode; v txd = 0 v [5] - - 75 ns t d(bge-busact) delay time from bge to bus active normal mode; v txd = 0 v [5] - - 75 ns t r(dif)(bus) bus differential rise time data_0 to data_1; 20 % to 80 % [5] 6-18.75ns t f(dif)(bus) bus differential fall time data_1 to data_0; 80 % to 20 % [5] 6-18.75ns ? t (r-f)(dif) difference between differential rise and fall time on bus; 80 % to 20 % [5] ? 3- 3 ns t f(bus)(idle-act) bus fall time from idle to active bus idle to data_0; ? 30 mv > v dif > ? 300 mv [5] [7] - - 30 ns t f(bus)(act-idle) bus fall time from active to idle data_1 to bus idle; 300 mv > v dif > 30 mv [5] [7] - - 30 ns t r(bus)(act-idle) bus rise time from active to idle data_0 to bus idle; ? 300 mv < v dif < ? 30 mv [5] [7] - - 30 ns wake-up detection t det(wake)data_0 data_0 wake-up detection time standby mode with no undervoltage on pin v cc ; ? 10 v ? v cm ? +15 v [3] [8] 1-4 ? s t det(wake)idle idle wake-up detection time standby mode with no undervoltage on pin v cc ; ? 10 v ? v cm ? +15 v [3] [8] 1-4 ? s tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 24 of 41 nxp semiconductors tja1083 flexray node transceiver t det(wake)tot total wake-up detection time standby mode with no undervoltage on pin v cc ; ? 10 v ? v cm ? +15 v [3] [8] 50 - 115 ? s t sup(int)wake wake-up interruption suppression time standby mode with no undervoltage on pin v cc ; ? 10 v ? v cm ? +15 v [3] [9] 130 - 1000 ns t d(wake-errn) delay time from wake-up to errn standby mode - - 100 ? s t d(wake-rxd) delay time from wake-up to rxd standby mode - - 100 ? s undervoltage t det(uv)(vcc) undervoltage detection time on pin v cc 0 v ? v io ? 5.5 v; v cc = 4.35 v 2-100 ? s t rec(uv)(vcc) undervoltage recovery time on pin v cc 0 v ? v io ? 5.5 v; v cc = 4.85 v 2-100 ? s t det(uv)(vio) undervoltage detection time on pin v io v th(det)por < v cc < 5.5 v; v io = 2.45 v 5-100 ? s t rec(uv)(vio) undervoltage recovery time on pin v io v th(det)por < v cc < 5.5 v; v io = 2.9 v 5-100 ? s activity detection t det(act)(bus) activity detection time on bus pins normal mode; v cm = 2.5 v; v dif : 0 mv ? 400 mv [3] [7] 100- 250ns t det(idle)(bus) idle detection time on bus pins normal mode; v cm = 2.5 v; v dif : 400 mv ? 0 mv [3] [7] 100- 200ns ?? t det(act-idle) ? active to idle detection time difference (absolute value) normal mode; on bus pins; v cm = 2.5 v [3] --150ns errn signaling t det(l)(sclk) low-level detection time on pin sclk normal or standby mode with no undervoltage on pin v io 95 - 310 ? s t errnl(min) minimum errn low time simple error indication mode; normal or standby mode 2-10 ? s t d(errdet-errnl) delay time from error detection to errn low all modes - - 100 ? s spi t d(scsnhl-sdol) scsn falling edge to sdo low-level delay time v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] --250ns t d(sclklh-sdodv) sclk rising edge to sdo data valid delay time v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] --200ns t d(scsnlh-sdoz) scsn rising edge to sdo three-state delay time v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] --500ns t sclk sclk period v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] 0.5 - 100 ? s table 12. dynamic characteristics ?continued all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? and c bus = 100 pf unless otherwise specified. all voltages are defined wi th respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 25 of 41 nxp semiconductors tja1083 flexray node transceiver [1] sum of txd rise and fall times (20 % to 80 %); t r(txd) + t f(txd) = max. 9 ns. [2] see figure 13 . [3] v cm is the bp/bm common mode voltage. [4] see figure 14 . [5] see figure 13 . [6] guaranteed by design. [7] v dif =v bp ? v bm . [8] see figure 8 . [9] see figure 9 . [10] see figure 11 . [11] load at end of 50 ? microstrip with a propagation delay of 1 ns; 20 % to 80 % and 80 % to 20 %. t spilead spi enable lead time v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] 250 - - ns t spilag spi enable lag time v uvd(vio) < v io < 5.5 v; 4.45 v < v cc < 5.5 v; c sdo = 50 pf [10] 250 - - ns rxd t r rise time 20 % to 80 %; c rxd = 15 pf [6] --9ns 20 % to 80 %; c rxd = 25 pf [6] --10.75ns t f fall time 80 % to 20 %; c rxd = 15 pf [6] --9ns 80 % to 20 %; c rxd = 25 pf [6] --10.75ns ? t (r-f) difference between rise and fall time c rxd = 15 pf [6] --5ns c rxd = 25 pf [6] --5ns c rxd = 10 pf; simulated [6] [11] --5ns t (r+f) sum of rise and fall time c rxd = 15 pf [6] - - 13 ns c rxd = 25 pf [6] - - 16.5 ns c rxd = 10 pf; simulated [6] [11] - - 16.5 ns bus error flag t d(norm-stb) normal mode to standby delay time bus error flag set 3 - 10 ? s t d(stb-norm) standby to normal mode delay time bus error flag set 3 - 10 ? s miscellaneous t detcl(txen) txen clamp detection time 650 - 2600 ? s t detcl(bge) bge clamp detection time 650 - 2600 ? s t d(txenh-rxdh) delay time from txen high to rxd high idle loop delay; normal mode; txd = low; v cm = 2.5 v; c rxd = 25 pf [3] --300ns table 12. dynamic characteristics ?continued all parameters are guaranteed for v cc = 4.45 v to 5.25 v; v io = 2.55 v to 5.25 v; t vj = ? 40 ? c to +150 ? c; r bus = 40 ? and c bus = 100 pf unless otherwise specified. all voltages are defined wi th respect to ground; positive currents flow into the ic. symbol parameter conditions min typ max unit xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 26 of 41 nxp semiconductors tja1083 flexray node transceiver fig 12. detailed timing diagram 20 % 80 % 0.5v io 0.5v io 0.5v io +300 mv -300 mv 0 v bge txen txd -300 mv -300 mv t d(txd-bus) t d(txd-bus t d(txen-busidle) t d(bge-busidle) t d(txen-busact) t d(bge-busact) 015aaa140 t d(bus-rxd) t d(bus-rxd) t d(bus-rxd) + t det(idle)(bus) t r(busact-busidle) t r(dif)(bus) t f(dif)(bus) rxd 0.5v io t f(busact-busidle) t d(bus-rxd) + t det(act)(bus) -30 mv -30 mv bp - bm +150 mv -150 mv tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 27 of 41 nxp semiconductors tja1083 flexray node transceiver (1) v o(dif)bus is the transmitter test signal. fig 13. transmitter timing diagram > 900 v o(dif)bus (1) (mv) txd 300 -300 < -900 100 % of v io 50 % of v io 0 % of v io t d(txd-bus) t 0 t 015aaa141 100 % 0 % 20 % 80 % t f(dif)(bus) t r(dif)(bus) t d(txd-bus) > 100 ns tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 28 of 41 nxp semiconductors tja1083 flexray node transceiver (1) ? v bus ? = 400 mv (min) to 3000 mv (max). (2) t r(bus) and t f(bus) are defined for v bus between ? 300 mv and +300 mv; t r(bus) = t f(bus) = 22.5 ns for ? v bus ? = 400 mv to 800 v; value will be lower for ? v bus ? > 800 mv. fig 14. normal receiver timing diagram 0 % v io 20 % v io 80 % v io 100 % v io 50 % v io t f(bus) (2) 22.5 ns max. t r(bus) (2) 22.5 ns max. -300 mv -v bus (1) 0 mv -150 mv +150 mv +300 mv +v bus (1) v bus t t d(bus-rxd)data_0 60 ns to 4340 ns t d(bus-rxd)data_1 t r(rxd) t f(rxd) rxd 015aaa142 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 29 of 41 nxp semiconductors tja1083 flexray node transceiver 11. test information fig 15. test circuit for measuring dynamic characteristics the waveforms of the applied transients are in accordance with iso 7637, test pulses 1, 2a, 3a and 3b. test conditions: normal mode: bus idle normal mode: bus active; txd at 5 mhz and txen at 1 khz fig 16. test circuit for measuring automotive transients 015aaa135 tja1083 v cc v io r bus c bus bp 13 114 12 4 bm rxd +5 v 100 nf c rxd 015aaa136 330 pf 330 pf iso 7637 pulse generator tja1083 v cc v io r bus c bus bp 13 114 12 bm +5 v 100 nf 15 pf rxd 4 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 30 of 41 nxp semiconductors tja1083 flexray node transceiver 12. package outline fig 17. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 31 of 41 nxp semiconductors tja1083 flexray node transceiver 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 32 of 41 nxp semiconductors tja1083 flexray node transceiver 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 18 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 3 and 14 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 18 . table 13. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 14. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 33 of 41 nxp semiconductors tja1083 flexray node transceiver for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. appendix 14.1 differences between tja1082 and tja1083 the main differences between the tja1083 and the tja1082 are: ? the tja1083 is epl v3.0.1 compliant wh ereas the tja1082 is epl v2.1 rev. b compliant ? the tja1083 is jaspar compliant (minimum transmitter output voltage of 900 mv) ? the tja1083 has a higher pulse immunity (iso7637) ? the tja1083 has improved emc behavior ? the bus load conditions for the static and dy namic characteristics are different in epl v3.0.1 compared to epl v2.1 rev. b: 40 ? to 55 ? for the static characteristics instead of 40 ? and 40 ? for the dynamic characteristics instead of 45 ? . msl: moisture sensitivity level fig 18. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 34 of 41 nxp semiconductors tja1083 flexray node transceiver 14.2 implementation of epl 3.0. 1 requirements in the tja1083 table 15. epl 3.0.1 implementation in tja1083 epl 3.0.1 tja1083 min max unit symbol min max unit dbdrxasym - 5 ns ?? t d(bus-rxd) ? 05 ns dbdrx10 - 75 ns t d(bus-rxd) -75ns dbdrx01 - 75 ns t d(bus-rxd) -75ns dbdrxai 50 275 ns t det(idle)(bus) + t d(bus-rxd) 100 275 ns dbdrxia 100 325 ns t det(act)(bus) + t d(bus-rxd) 100 325 ns dbdtxasym - 4 ns ?? t d(txd-bus) ? 04 ns dbdtx10 - 75 ns t d(txd-bus) -60ns dbdtx01 - 75 ns t d(txd-bus) -60ns dbdtxai - 75 ns t d(txen-busidle) -75ns dbdtxia - 75 ns t d(txen-busact) -75ns dbustxai - 30 ns t r(bus)(act-idle) -30ns dbustxia - 30 ns t f(bus)(idle-act) -30ns dbustx01 6 18.75 ns t r(dif)(bus) 6 18.75 ns dbustx10 6 18.75 ns t f(dif)(bus) 6 18.75 ns ubdtx active 600 2000 mv v oh(dif) 900 2000 mv ubdtx idle 030mv ?v o(idle)(dif) ? 025mv uv dig-out-high 80 100 % v oh(rxd) v io ? 0.4 v io v v oh(errn) v io ? 0.4 v io v uv dig-out-low -20%v ol(rxd) -0.4v v ol(errn) -0.4v uv dig-in-high -70%v ih(txen) 0.7v io 5.5 v v ih(stbn) 0.7v io 5.5 v v ih(bge) 0.7v io 5.5 v uv dig-in-low 30 - % v il(txen) ? 0.3 +0.3v io v v il(stbn) ? 0.3 +0.3v io v v il(bge) ? 0.3 +0.3v io v udata0 ? 300 ? 150 mv v il(dif) ? 300 ? 150 mv udata1 150 300 mv v ih(dif) 150 300 mv udata1-|udata0| ? 30 30 mv ?? v i(dif)(h-l) ? -30mv dbdactivitydetection 100 250 ns t det(act)(bus) 100 250 ns dbdidledetection 50 200 ns t det(idle)(bus) 100 200 ns r cm1 , r cm2 10 40 k ? r i(bp) , r i(bm) 10 40 k ? ucm ? 10 15 v v cm [1] ? 10 +15 v ibm gndshortmax -60ma ?i o(sc)(bm) ? -60ma ibp gndshortmax -60ma ?i o(sc)(bp) ? -60ma ibm bat48shortmax -72ma ?i o(sc)(bm) ? -72ma ibp bat48shortmax -72ma ?i o(sc)(bp) ? -72ma ibm bat27shortmax -60ma ?i o(sc)(bm) ? -60ma tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 35 of 41 nxp semiconductors tja1083 flexray node transceiver ibp bat27shortmax -60ma ?i o(sc)(bp) ? -60ma ubias, non low-power modes 1800 3200 mv v o(idle)(bp) , v o(idle)(bm) [2] 1800 3150 mv ubias, low-power modes -200 200 mv v o(idle)(bp) , v o(idle)(bm) [3] ? 0.1 +0.1 v dwu 0detect 14 ? st det(wake)data_0 14 ? s dwu idledetect 14 ? st det(wake)idle 14 ? s dwu timeout 48 140 ? st det(wake)tot 50 115 ? s ubduvv cc 4- vv uvd(vcc) 4.45 4.729 v dbduvv cc - 1000 ms t det(uv)(vcc) 2100 ? s ibp leak -25 ? ai li(bp) -5 +5 ? a ibm leak -25 ? ai li(bm) -5 +5 ? a functional class ?bus driver logic level adaptation? implemented; see section 2.4 functional class ?bus driver - bus guardian interface? implemented; see section 2.4 device qualification according to aec-q100 (rev. f) see section 2.1 t amb_class1 ? 40 125 ?ct amb ? 40 +125 ?c dbdtxdm ? 50 50 ns ? t d(txen-bus) ? 50 50 ns ibm -5vshortmax -60ma ?i o(sc)(bm) ? -60ma ibp -5vshortmax -60ma ?i o(sc)(bp) ? -60ma ibm bpshortmax -60ma ?i o(sc)(bm) ? -60ma ibp bmshortmax -60ma ?i o(sc)(bp) ? -60ma ibm bat60shortmax -90ma ?i o(sc)(bm) ? -72ma ibp bat60shortmax -90ma ?i o(sc)(bp) ? -72ma uuv io 2- vv uvd(vio) 2.55 2.774 v dbduvv io - 1000 ms t det(uv)(vio) 5100 ? s dbdwakeupreaction remote - 100 ? st d(wake-errn) , t d(wake-rxd) -100 ? s dbdtxactivemax 650 2600 ? st detcl(txen) 650 2600 ? s dbdmodechange 100 100 ? st d(norm-stb) , t d(stb-norm) 310 ? s dbderrn stable 110 ? st errn(min) 210 ? s dreactiontime errn - 100 ? st d(errdet-errnl) -100 ? s udata0_lp ? 400 ? 100 mv v il(dif) ? 400 ? 100 mv dwu interrupt 0.13 1 ? st sup(int)wake 130 1000 ns ubdlogic_1 - 60 % v ih(txd) 0.6v io 5.5 v ubdlogic_0 40 - % v il(txd) ? 0.3 0.4v io v dbdrv cc -10mst rec(uv)(vcc) 2100 ? s dbdrv io -10mst rec(uv)(vio) 5100 ? s ibp leakgnd - 1600 ? ai li(bp) ? 1600 1600 ? a ibm leakgnd - 1600 ? ai li(bm) ? 1600 1600 ? a functional class ?bus driver remote wakeup? implemented; see section 2.4 table 15. epl 3.0.1 implementation in tja1083 epl 3.0.1 tja1083 min max unit symbol min max unit tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 36 of 41 nxp semiconductors tja1083 flexray node transceiver [1] v cm is the bp/bm common mode voltage, (v bp +v bm ) / 2, and is specified in conditions column of parameters v ih(dif) and v il(dif) for pins bp and bm; see table 11 . v cm is tested on a receiving bus driver with a transmitti ng bus driver that has a ground offset voltage in the range ? 12.5 v to +12.5 v and transmits a 50/50 pattern. [2] min. value: v o(idle)(bp) = v o(idle)(bm) = 0.4v cc = 0.4 ? 4.5 v = 1800 mv; max value: v o(idle)(bp) = v o(idle)(bm) = 0.6v cc = 0.6 ? 5.25 v = 3150 mv; the nominal voltage is 2500 mv. [3] the normal voltage is 0 mv. [4] power-off mode. functional class ?bus driver increased voltage amplitude transmitter? implemented; see section 2.4 uesd ext 6- kv ?v esd ? : hbm on pins bp and bm to gnd -8kv uesd int 2- kv ?v esd ? : hbm on any other pin -4kv uesd iec 6- kv ?v esd ? : iec61000-4-2 on pins bp and bm to gnd -8kv dbdrxd r15 + dbdrxd f15 -13ns ?t (r+f) (pin rxd; 15 pf load) - 13 ns ? dbdrxd r15 ? dbdrxd f15 ? -5ns ?? t (r-f) ? (pin rxd; 15 pf load) - 5 ns c_bdtxd - 10 pf c i(txd) -10pf dbdtxrxai - 325 ns t d(txenh-rxdh) -300ns uv dig-out-uv - 500 mv v o(uvvio)rxd -500mv v o(uvvio)errn -500mv v o(uvvio)sdo -500mv uv dig-out-off product specific v ol(rxd) [4] v io ? 500 v io mv v ol(errn) [4] -500mv v ol(sdo) [4] -500mv r bdtransmitter product specific z o(tx)(eq) 10 600 ? rxd signal sum of rise and fall time at tp4_cc - 16.5 ns ?t (r+f) (pin rxd; 10 pf load; simulated) -16.5ns dbdrxd r25 + dbdrxd f25 - 16.5 ns ?t (r+f) (pin rxd; 25 pf load) - 16.5 ns ? dbdrxd r25 ? dbdrxd f25 ? -5ns ?? t (r-f) ? (pin rxd; 25 pf load) - 5 ns dbustxdif - 3 ns ?? t (r-f)(dif) ? -3ns rxd signal difference of rise and fall time at tp4_cc -5ns ?? t (r-f) ? (pin rxd; 10 pf load; simulated) -5ns table 15. epl 3.0.1 implementation in tja1083 epl 3.0.1 tja1083 min max unit symbol min max unit tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 37 of 41 nxp semiconductors tja1083 flexray node transceiver 15. abbreviations 16. references [1] epl ? flexray communications system electrical physical layer specification version 3.0.1 (expected to be released by the end of 2009) [2] an ? application hint an10365 - surface mount reflow soldering description table 16. abbreviations abbreviation description cdm charged device model ecu electronic control unit emc electromagnetic compatibility eme electromagnetic emission emi electromagnetic immunity esd electrostatic discharge hbm human body model jaspar japan automotive soft ware platform architecture mm machine model pwon power-on tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 38 of 41 nxp semiconductors tja1083 flexray node transceiver 17. revision history table 17. revision history document id release date data sheet status change notice supersedes tja1083 v.1 20121010 product data sheet - - tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 39 of 41 nxp semiconductors tja1083 flexray node transceiver 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. tja1083 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 10 october 2012 40 of 41 nxp semiconductors tja1083 flexray node transceiver export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 18.4 licenses 18.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp ics with flexray functionality this nxp product contains functionalit y that is compliant with the flexray specifications. these specifications and the material contained in them, as released by the flexray consortium, are for the purpose of information only. the flexray consortium and the companies that have contributed to the specifications shall not be liable for any use of the specifications. the material contained in these specific ations is protect ed by copyright and other types of intellectual property rights. the commercial exploitation of the material contained in the specifications requires a license to such intellectual property rights. these specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. for any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. the flexray specifications ha ve been developed for automotive applications only. they have neither been developed nor tested for non-automotive applications. the word flexray and the flexray logo are registered trademarks. nxp semiconductors tja1083 flexray node transceiver ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 october 2012 document identifier: tja1083 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 optimized for time triggered communication systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 low-power management . . . . . . . . . . . . . . . . . 1 2.3 diagnosis and robustness . . . . . . . . . . . . . . . . 2 2.4 functional classes according to flexray electrical physical layer specification v3.0.1. . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.1 bus activity and idle detection . . . . . . . . . . . . . 7 6.1.2 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.3 power-off mode . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.4 state transitions . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 power-up and power-down behavior . . . . . . . . 9 6.2.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.2 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 remote wake-up . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 bus wake-up via wake-up pattern. . . . . . . . . . 11 6.3.2 bus wake-up via dedicated flexray data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 bus error detection . . . . . . . . . . . . . . . . . . . . . 12 6.5 fail silent behavior . . . . . . . . . . . . . . . . . . . . . 12 6.6 tja1083 flags. . . . . . . . . . . . . . . . . . . . . . . . . 12 6.7 tja1083 status register . . . . . . . . . . . . . . . . . 13 6.8 error signaling . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8.1 spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8.2 simple error indication mode . . . . . . . . . . . . . 15 6.9 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 8 thermal characteristics . . . . . . . . . . . . . . . . . 17 9 static characteristics. . . . . . . . . . . . . . . . . . . . 18 10 dynamic characteristics . . . . . . . . . . . . . . . . . 23 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 29 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 13 soldering of smd packages . . . . . . . . . . . . . . 31 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 31 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 31 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 32 14 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.1 differences between tja1082 and tja1083. 33 14.2 implementation of epl 3.0.1 requirements in the tja1083. . . . . . . . . . . . . . . . . . . . . . . . 34 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 38 18 legal information . . . . . . . . . . . . . . . . . . . . . . 39 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 39 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.4 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 18.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 contact information . . . . . . . . . . . . . . . . . . . . 40 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 |
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